Gate signal line drive circuit

ABSTRACT

A gate signal line drive circuit whose power consumption is reduced, is provided. In the gate signal line drive circuit having plural basic circuits outputting respective gate signals, each basic circuit includes a high voltage application switching element to which a first basic clock signal having high voltage in a signal high period is input, a low voltage application switching element that turns on at timing starting a signal low period, and outputs a low voltage, and a first low voltage application on control element having an input terminal to which a second basic clock signal subsequent to the first basic clock signal is input, and which turns on according to the signal high period, and outputs the voltage of the second basic clock signal to the control terminal of the low voltage application switching element.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is a continuation of U.S. patent application Ser. No.14/497,388, filed on Sep. 26, 2014. Further, this application claimspriority from Japanese application No. 2013-202602, filed on Sep. 27,2013, the contents of which are hereby incorporated by reference intothis application.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a gate signal line drive circuit and adisplay device using the drive circuit. In particularly, the presentinvention relates to a reduction in power consumption in a gate signalline drive circuit.

2. Description of the Related Art

Up to now, for example, liquid crystal display devices may employ asystem in which a shift register circuit disposed in a gate signal linedrive circuit that scans gate signal lines is formed on the samesubstrate as that of thin film transistors (hereinafter referred to as“TFT”) which are arranged in a pixel area of a display screen, that is,a shift register built-in system.

The shift register circuit disposed in the gate signal line drivecircuit outputs gate signals G_(n) which become high voltage in a signalhigh period which is cyclically repeated, and low voltage in a signallow period which is a period other than the signal high period tocorresponding gate signal lines.

FIG. 16 is a circuit diagram illustrating a basic circuit of a shiftregister circuit in a related art. A transistor T5 is a high voltageapplication switching element that applies a high voltage to the gatesignal lines according to the signal high period. A basic clock signalV_(n) is input to an input terminal of the transistor T5. The basicclock signal V_(n) is a clock signal repeated, for example, with fourclocks as one cycle, and becomes high voltage in a clock which is asignal high period (period P3) of a gate signal G_(n) as with a basicclock signal V_(n) according to the present invention illustrated inFIG. 5.

It is assumed that a voltage to be applied to a gate of the transistorT5 is a node N1, and a voltage to be applied to a gate of a transistorT6 is a node N2. The node N1 and the node N2 become high voltage and lowvoltage in a period P2 to a period P4, respectively, as with a node N1and a node N2 according to the present invention illustrated in FIG. 5.In the above period, the transistor T5 becomes in an on state, andoutputs a voltage of the basic clock signal V_(n) to an output terminalOUT connected to the gate signal line. In the period, the transistor T6is maintained in an off state.

SUMMARY OF THE INVENTION

The basic clock signal V_(n) is input to the input terminal of thetransistor T5 illustrated in FIG. 16. The transistor T5 is maintained inthe off state according to the signal low period. However, since acharge and discharge current flows in the transistor T5 due to aparasitic capacitance provided in the transistor T5 every time a voltageof the basic clock signal V_(n) changes, a power consumption increases.

Since the parasitic capacitance can be reduced with a reduction in theelement size of the transistor T5, the charge and discharge currentgenerated in the transistor T5 can be suppressed. The transistor T6becomes in the off state before and after the signal high period (periodP2 to period P4 illustrated in FIG. 5), and a load caused by a voltagechange of the gate signal line is exerted on the transistor T5 that isin the on state.

FIG. 17 is a diagram illustrating a signal waveform of the gate signalin the related art. FIG. 17 illustrates signal waveforms of a gatesignal G_(n) output by a basic circuit of a shift register circuitaccording to the related art illustrated in FIG. 16. The signalwaveforms of the gate signal G_(n) illustrated in FIG. 17 are newlymeasured for the purpose of evaluating the gate signal related to therelated art by the present inventors. FIG. 17 illustrates the signalwaveforms when a channel width of the transistor T5 is reduced from 3500μm to 1500 μm at the intervals of 500 μm. In this example, it is assumedthat a signal waveform in which the gate signal G_(n) changes from thelow voltage to the high voltage is a rising waveform, and a signalwaveform in which the gate signal G_(n) changes from the high voltage tothe low voltage is a falling waveform. With a reduction in the elementsize of the transistor T5, the rising waveforms and the fallingwaveforms of the gate signal G_(n) change in directions indicated byarrows in the figure, and blunting increases. Even if the risingwaveform of the gate signal G_(n) is blunted, it is sufficient that thegate signal G_(n) rises to a sufficiently saturated state so that aswitching transistor of each pixel circuit sufficiently turns on attiming when the pixel circuit writes the pixel. However, as indicated bya dashed line in FIG. 17, if the falling waveform of the gate signalG_(n) is increasingly blunted, the gate signal G_(n) does notsufficiently drop to the low voltage even after the pixel circuit writesthe pixel, the pixel voltage held by the pixel circuit is varied byrewrite without sufficiently turning off the switching transistor of thepixel circuit, and the quality of a display screen is degraded, forexample, the brightness is reduced.

JP 2011-085663 A discloses a signal output circuit 241 having atransistor TG that changes an output G_(i) (gate signal) to low attiming when a clock V_(i) input to a transistor T5, which is a highvoltage application switching element, changes from high to low (referto FIG. 4 in JP 2011-85663 A). An output G_(i+4) in a subsequent stageis input to a gate of a transistor TG. At a time t4 (refer to FIG. 5 inJP 2011-85663 A) when the clock V_(i) changes from high to low, theoutput G_(i+4) changes from low to high, the transistor TG is renderedconductive, and the output Gi is connected to VGPL which is low. Thetransistor TG functions to change the output G_(i) from high to low.

However, as with the rising waveform of the gate signal as illustratedin FIG. 17, since the rising waveform of the output G_(i) is blunted,the output G_(i) does not sufficiently change to high at the time ofrising in fact. Hence, the conduction of the transistor TG is notsufficient, and the transistor TG cannot sufficiently contribute to asufficient change of the output G_(i) from high to low at the time ofrising. For that reason, most of a load generated by a voltage change ofthe gate signal line at the time of rising is still exerted on thetransistor T5. That is, it is still difficult to reduce the element sizeof the transistor T5 by only adding the transistor TG.

The present invention has been made in view of the above problem, andtherefore aims at providing a gate signal line drive circuit thatreduces a power consumption, and a display device using the gate signalline drive circuit.

(1) According to the present invention, there is provided a gate signalline drive circuit including a plurality of basic circuits that outputrespective gate signals which become high voltage in a signal highperiod which is cyclically repeated, and become low voltage in a signallow period which is a period other than the signal high period tocorresponding gate signal lines. Each of the basic circuits includes: ahigh voltage application switching element having an input terminal anda control terminal in which a first basic clock signal that is repeatedwith m clocks (m is an integer equal to or higher than 3) as one cycle,and becomes high voltage in a clock which is the signal high period, andbecomes low voltage in the other clocks is input to the input terminalof the high voltage application switching element, and the high voltageis applied to the control terminal of the high voltage applicationswitching element according to the signal high period, to output avoltage of the first basic clock signal to the corresponding gate signalline; a low voltage application switching element having a controlterminal to which the high voltage is applied at timing to change fromthe signal high period to the signal low period, to output the lowvoltage to the corresponding gate signal line; and a first low voltageapplication on control element having an input terminal and a controlterminal in which a second basic clock signal that is repeated with them clocks as one cycle, and becomes high voltage in a clock subsequent tothe clock in which the first basic clock signal becomes high voltage,and becomes low voltage in the other clocks is input to the inputterminal of the first low voltage application on control element, andthe high voltage is applied to the control terminal of the first lowvoltage application on control element according to the signal highperiod, to output a voltage of the second basic clock signal to thecontrol terminal of the low voltage application switching element atleast at timing when the second basic clock signal changes from the lowvoltage to the high voltage.

(2) In the gate signal line drive circuit according to the above item(1), the plurality of basic circuits may include a first basic circuit,and a second basic circuit, the signal high period of the second basiccircuit may start within one clock after a start of the signal highperiod of the first basic circuit, and the control terminal of the highvoltage application switching element in the second basic circuit may beconnected to the control terminal of the low voltage application oncontrol element in the first basic circuit.

(3) In the gate signal line drive circuit according to the above item(1) or (2), each of the basic circuits may further include: a first lowvoltage application off control element that turns on after the firstlow voltage application on control element outputs the high voltage ofthe second basic clock signal to the control terminal of the low voltageapplication switching element, and outputs the low voltage to thecontrol terminal of the low voltage application switching element.

(4) In the gate signal line drive circuit according to the above item(3), a third basic clock signal that is repeated with the m clocks asone cycle, and becomes high voltage in a clock subsequent to the clockin which the second basic clock signal becomes high voltage, and becomeslow voltage in the other clocks may be input to the control terminal ofthe first low voltage application off control element, and the first lowvoltage application off control element may become in the on state whenthe third basic clock signal becomes high voltage.

(5) In the gate signal line drive circuit according to any one of theabove items (1) to (4), m of the m clocks is an integer of 4 or higher,each of the basic circuits further comprises a second low voltageapplication on control element having an input terminal and a controlterminal in which a fourth basic clock signal that is repeated with them clocks as one cycle, and becomes high voltage in a clock previous tothe clock in which the first basic clock signal becomes high voltage,and becomes low voltage in the other clocks is input to the inputterminal of the second low voltage application on control element, andthe high voltage is applied to the control terminal of the second lowvoltage application on control element according to the signal highperiod, to output a voltage of the fourth basic clock signal to thecontrol terminal of the low voltage application switching element atleast at timing when the fourth basic clock signal changes from the lowvoltage to the high voltage, forward scanning in which the gate signalsoutput by the plurality of basic circuits become the signal high periodin a forward order is driven, and the fourth basic clock signal is inputto the input terminal of the first low voltage application on controlelement instead of the second basic clock signal, and the second basicclock signal is input to the input terminal of the second low voltageapplication on control element instead of the fourth basic clock signal,to drive reverse scanning in which the gate signals output by theplurality of basic circuits become the signal high period in a reverseorder of the forward order.

(6) According to the present invention, there may be provided a displaydevice including the gate signal line drive circuit according to any oneof the above items (1) to (5).

According to the present invention, there are provided the gate signalline drive circuit whose power consumption is reduced, and the displaydevice using the drive circuit.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a perspective view illustrating an overall liquid crystaldisplay device according to a first embodiment of the present invention;

FIG. 2 is a conceptual diagram illustrating an equivalent circuit of aTFT substrate according to the first embodiment of the presentinvention;

FIG. 3 is a block diagram illustrating a shift register circuitaccording to the first embodiment of the present invention;

FIG. 4 is a circuit diagram of an n-th basic circuit according to thefirst embodiment of the present invention;

FIG. 5 is a timing chart representing drive operation of a gate signalline drive circuit according to the first embodiment of the presentinvention;

FIG. 6 is a diagram illustrating a signal waveform of a gate signalaccording to the first embodiment of the present invention;

FIG. 7 is a schematic diagram illustrating a configuration of a gatesignal line drive circuit according to a second embodiment of thepresent invention;

FIG. 8 is a circuit diagram illustrating a basic circuit according tothe second embodiment of the present invention;

FIG. 9 is a timing chart representing drive operation of the gate signalline drive circuit according to the second embodiment of the presentinvention;

FIG. 10 is a circuit diagram of an n-th basic circuit according to athird embodiment of the present invention;

FIG. 11 is a timing chart representing drive operation of a gate signalline drive circuit according to the third embodiment of the presentinvention;

FIG. 12 is a circuit diagram of an n-th basic circuit according to afourth embodiment of the present invention;

FIG. 13 is a timing chart representing drive operation of a gate signalline drive circuit in forward scanning according to the fourthembodiment of the present invention;

FIG. 14 is a timing chart representing drive operation of the gatesignal line drive circuit in reverse scanning according to the fourthembodiment of the present invention;

FIG. 15 is a conceptual diagram of an equivalent circuit of a TFTsubstrate provided in a liquid crystal display device according toanother example of the embodiment of the present invention;

FIG. 16 is a circuit diagram of a basic circuit of a shift registercircuit in a related art; and

FIG. 17 is a diagram illustrating a signal waveform of a gate signal inthe related art.

DETAILED DESCRIPTION OF THE INVENTION

Hereinafter, embodiments of the present invention will be described withreference to the accompanying drawings specifically and in detail. Inall of drawings illustrating the embodiments, members having the samefunction are denoted by identical symbols, and a repetitive descriptionthereof will be omitted. Also, the drawings described below illustrateexamples of the embodiments, and sizes of the drawings do not alwaysmatch reduced sizes described in the examples.

First Embodiment

A display device according to a first embodiment of the presentinvention is, for example, an IPS (in-plane switching) liquid crystaldisplay device. FIG. 1 is a perspective view of an overall liquidcrystal display device according to the first embodiment. As illustratedin FIG. 1, the liquid crystal display device according to the embodimentincludes a TFT substrate 102 on which gate signal lines 105, videosignal lines 107, pixel electrodes 110, a common electrode 111, and TFTs109, which will be describe later, are arranged, a filter substrate 101that faces the TFT substrate 102, and has color filters disposedthereon, a liquid crystal material that is sealed in an area sandwichedbetween those substrates, and a backlight 103 that is located in contactwith a side of the TFT substrate 102 opposite to the filter substrate101 side.

FIG. 2 is a conceptual diagram illustrating an equivalent circuit of theTFT substrate 102 according to this embodiment. Referring to FIG. 2, alarge number of the gate signal lines 105 connected to a gate signalline drive circuit 104 extend at regular intervals in a lateraldirection of the figure on the TFT substrate 102.

The gate signal line drive circuit 104 includes a shift register controlcircuit 114 and a shift register circuit 112, and the shift registercontrol circuit 114 outputs a control signal 115, which will bedescribed later, to the shift register circuit 112.

The shift register circuit 112 includes a plurality of basic circuits113 in correspondence with the plural gate signal lines 105. Forexample, if there are 800 gate signal lines 105, 800 basic circuits 113are provided in the shift register circuit 112, likewise. Each of thebasic circuits 113 outputs agate signal that becomes high voltage in asignal high period cyclically repeated, and becomes low voltage in aperiod (signal low period) other than the signal high period to thecorresponding gate signal line 105 through the control signal 115 inputfrom the shift register control circuit 114. That is, each of the basiccircuits 113 outputs, to a corresponding gate signal line 105, the highvoltage in the signal high period, and the low voltage in the signal lowperiod. For simplification of description, in FIG. 2, the shift registercircuit 112 is illustrated on only a left side of FIG. 2. However, infact, an odd shift register circuit that outputs gate signals to oddgate signal lines 105 (400) is located on a right side of FIG. 2, and aneven shift register circuit that outputs the gate signals to even gatesignal lines 105 (400) is located on a left side of FIG. 2.

Also, a large number of the video signal lines 107 connected to a datadrive circuit 106 extend at regular intervals in a longitudinaldirection of FIG. 2. Pixel areas arranged in a grid are partitioned bythe gate signal lines 105 and the video signal lines 107. Also, commonsignal lines 108 extend in parallel to the respective gate signal lines105 in the lateral direction of FIG. 2.

The TFT 109 (switching transistor) is formed in a corner of each of thepixel areas partitioned by the gate signal lines 105 and the videosignal lines 107, and connected to the corresponding video signal line107 and the corresponding pixel electrode 110. Further, the gate of theTFT 109 is connected to the gate signal lines 105. Also, a commonelectrode 111 is formed in each of the pixel areas so as to face thepixel electrode 110.

In the above circuit configuration, a reference voltage is applied tothe common electrode 111 in each of the pixel circuits through thecorresponding common signal line 108. Also, a gate voltage isselectively applied to a gate of each of the TFTs 109 through thecorresponding gate signal line 105, to thereby control a current thatflows in the TFT 109. A voltage of a video signal supplied to the videosignal line 107 is applied to the pixel electrode 110 through the TFT109 having the gate applied with the gate voltage. With the aboveoperation, a potential difference is generated between the pixelelectrode 110 and the common electrode 111 to control orientations ofliquid crystal molecules, as a result of which the degree of shieldingof light from the backlight 103 is controlled to display an image.

FIG. 3 is a block diagram illustrating the shift register circuit 112according to this embodiment. For example, if 800 gate signal lines 105are present, 800 basic circuits 113 corresponding to the respective 800gate signal lines 105 are provided in the shift register circuit 112. Asdescribed above, 400 odd basic circuits corresponding to the respectiveodd gate signal lines 105 (400) are located on a right side of a displayarea 120, and 400 even basic circuits corresponding to the respectiveeven gate signal lines 105 (400) are located on a left side of thedisplay area 120. FIG. 3 illustrates eight basic circuits 113 of n=1 to8 among 800 basic circuits 113. In FIG. 3, an n-th basic circuit isgenerally referred to as “basic circuit 113-n”.

The control signal 115 output to the shift register circuit 112 by theshift register control circuit 114 includes basic clock signals V₁ toV₈, a low voltage line V_(GtT) that applies the low voltage, andauxiliary signals V_(ST1), V_(ST2).

Generally, m-phase basic clock signals will be described. The m-phasebasic clock signals are clock signals different in phase from each otherin a given cycle T. When it is assumed that a cycle of the basic clocksignal is T, one cycle T of the m-phase basic clock signals issubdivided into m periods of T/m. When a period of T/m is called “oneclock”, one cycle T includes m clocks. Each clock signal of the m-phasebasic clock signals is a signal that becomes high voltage in one clock,and becomes low voltage in the other clocks, in each cycle T.

In this embodiment, four-phase basic clock signals V₁, V₃, V₅, and V₇become high voltage in the stated order for each of the clocks in onecycle T, and become low voltage in the other clocks. Four-phase basicclock signals V₂, V₄, V₆, and V₈ are clock signals that become highvoltage with a delay of half clock from the four-phase basic clocksignals V₁, V₃. V₅, and V₇, respectively. When it is assumed that aperiod during which a video signal is written per pixel is onehorizontal scanning period (1H period), one clock of the basic clocksignal has a length of two horizontal scanning periods (2H periods).That is, in the gate signal line drive circuit 104 according to thisembodiment, the signal high periods of the gate signals G_(n) andG_(n+1) that are supplied to the respective two adjacent gate signallines 105 overlap with each other by half clocks (1H period), to conduct1H overlap drive.

As illustrated in basic circuits 113-1 and 113-2 in FIG. 3, each of thebasic circuits 113 illustrated in FIG. 3 includes seven input terminalsIN1, IN2, IN3, IN4, IN5, IN6, IN7, and two output terminals OUT, OUT2.The gate signal G_(n) is output to the display area 120 from the outputterminal OUT of an n-th basic circuit 113-n. Also, the output terminalOUT2 is connected to a node N1 which will be described later.

The basic clock signal V_(n) is input to the input terminal IN1 of then-th basic circuit 113-n, a basic clock signal V_(n+2) is input to theinput terminal IN5, and a basic clock signal V_(n+4) is input to theinput terminals IN2 and IN7. FIG. 3 illustrates a first basic circuit113-1 as an example of the n-th basic circuit 113-n. That is, a basicclock signal input to the input terminal IN1 of the first basic circuit113-1 is indicated as the basic clock signal V_(n)(=V₁), a basic clocksignal input to the input terminal IN5 is indicated as the basic clocksignal V_(n+2)(=V₃), and a basic clock signal input to the inputterminals IN2 and IN7 is indicated as the basic clock signalV_(n+4)(=V₅). Also, a gate signal G_(n−2) output by an (n−2)-th basiccircuit 113-(n−2) is input to the input terminal IN3 of the n-th basiccircuit 113-n, and a gate signal G_(n+4) output by an (n+4)-th basiccircuit 113-(n+4) is input to the input terminal IN4. A node N1 _(n+2)output from the output terminal OUT2 of the (n+2)-th basic circuit113-(n+2) is connected to the input terminal IN6 of the n-th basiccircuit 113-n.

“n” of the basic clock signal V_(n) corresponds to “n” of the n-th basiccircuit 113-n. However, since “n” of a real basic clock signal V_(n)takes only any one of values 1 to 8, if the value of “n” of the basiccircuit 113 exceeds 8, the value can be subjected to conversion with theuse of V_(n−8)=V_(n)=V_(n|8). The basic clock signal V_(n) indicates anybasic clock signal of V₁ to V₈. That is, the “n” of the basic clocksignal V_(n) can be converted by [{(n−1) mod 8}+1]. For example, whenn=405 is met, the basic clock signal V_(n) is V₅, and the basic clocksignal V_(n+4) is V₁.

Also, because the input terminals IN3 of the first basic circuit 113-1and the second basic circuit 113-2 have no respective corresponding gatesignals, auxiliary signals V_(ST1) and V_(ST2) are input to those inputterminals IN3. Also, because the input terminals IN4 of a 797^(th) basiccircuit 113-797 to an 800^(th) basic circuit 113-800 have no respectivecorresponding gate signals, dummy circuits that are an 801^(st) basiccircuit to an 804^(th) basic circuit are provided. Output signals G₈₀₁to G₈₀₄ which are outputs of the 801^(st) basic circuit (dummy circuit)to the 804^(th) basic circuit (dummy circuit) are input to the inputterminals IN4 of the 797^(th) basic circuit 113-797 to the 800^(th)basic circuit 113-800, respectively.

FIG. 4 is a circuit diagram of the n-th basic circuit 113-n according tothis embodiment. All of transistors illustrated in the figure are NMOStransistors (n-channel transistors). The n-th basic circuit 113-naccording to this embodiment includes a gate signal line low voltageholding circuit 11, a gate signal line high voltage supply circuit 12, anode N1 low voltage holding circuit 13, and a gate signal line lowvoltage supply circuit 14. The gate signal line high voltage supplycircuit 12 includes a transistor T5 which is a high voltage applicationswitching element, and a boost capacitor C1. The input terminal IN1 isconnected to an input terminal of the transistor T5, and an outputterminal OUT (corresponding gate signal line 105) is connected to anoutput terminal of the transistor T5. Since the basic clock signal V_(n)(first basic clock signal) is input to the input terminal IN1, the basicclock signal V_(n) (first basic clock signal) is input to the inputterminal of the transistor T5. The basic clock signal V_(n) is a clocksignal that becomes high voltage in the signal high period of the gatesignal G_(n). The transistor T5 becomes in the on state according to thesignal high period, and the transistor T5 that is in an on state outputsa voltage of the basic clock signal V_(n) to the output terminal OUT.That is, the voltage of the basic clock signal V_(n) is output to thecorresponding gate signal line 105 from the output terminal OUT of then-th basic circuit 113-n as the gate signal G_(n). The transistor T5becomes in the off state according to the signal low period. In thisexample, it is assumed that a voltage to be applied to the gate (controlterminal: switch) of the transistor T5 (high voltage applicationswitching element) is the node N1.

The gate signal line low voltage holding circuit 11 becomes in the onstate according to the signal low period, and applies a low voltage tothe output terminal OUT (corresponding gate signal line 105). Also, thegate signal line low voltage holding circuit 11 becomes in the off stateaccording to the signal high period. The gate signal line low voltageholding circuit 11 includes a transistor T6 which is a low voltageholding switching element. A low voltage line V_(GL) is connected to aninput terminal of the transistor T6, and the output terminal OUT(corresponding gate signal line 105) is connected to an output terminalof the transistor T6. It is assumed that a voltage applied to the gate(control terminal) of the transistor T6 (low voltage holding switchingelement) is the node N2.

The gate signal line low voltage supply circuit 14 includes a lowvoltage application switching element T5A, a first low voltageapplication on control element T5B, and a first low voltage applicationoff control element T5C. The low voltage line V_(GL) is connected to aninput terminal of the transistor T5A, and the output terminal OUT(corresponding gate signal line 105) is connected to an output terminalof the transistor T5A. It is assumed that a voltage to be applied toagate (control terminal) of the transistor T5A (low voltage applicationswitching element) is a node N3. Hereinafter, the nodes N1, N2, and N3of the n-th basic circuit 113-n are denoted as nodes N1 _(n), N2 _(n),and N3 _(n).

The input terminal IN5 is connected to an input terminal of thetransistor T5B (first low voltage application on control element), thenode N3 is connected to an output terminal of the transistor T5B, andthe input terminal IN6 is connected to a gate (control terminal) of thetransistor T5B. As illustrated in FIG. 3, the basic clock signal V_(n+2)(second basic clock signal) is input to the input terminal IN5, and thenode N1 _(n+2) of the (n+2)-th basic circuit 113-(n+2) is connected tothe input terminal IN6. Hence, the basic clock signal V_(n+2) is inputto the input terminal of the transistor T5B. Also, the low voltage lineV_(GL) is connected to an input terminal of the transistor T5C (firstlow voltage application off control element), the node N3 is connectedto an output terminal of the transistor T5C, and the input terminal IN7is connected to a gate (control terminal) of the transistor T5C. Asillustrated in FIG. 3, since the basic clock signal V_(n+4) (third basicclock signal) is input to the input terminal IN7, the basic clock signalV_(n+4) is input to the gate of the transistor T5C. In this example, thebasic clock signal V_(n+2) (second basic clock signal) is a clock signalwhich becomes high voltage in a clock subsequent to the clock in whichthe basic clock signal V_(n) (first basic clock signal) becomes highvoltage, and the basic clock signal V_(n+4) (third basic clock signal)is a clock signal which becomes high voltage in a clock subsequent tothe clock in which the basic clock signal V_(n+2) (second basic clocksignal) becomes high voltage.

The node N1 low voltage holding circuit 13 becomes in the on stateaccording to the signal low period, and applies the low voltage to thenode N1. Also, the node N1 low voltage holding circuit 13 becomes in theoff state according to the signal high period. The node N1 low voltageholding circuit 13 includes a transistor T2. The low voltage line V_(GL)is connected to an input terminal of the transistor T2, the node N1 isconnected to an output terminal of the transistor T2, and the node N2 isconnected to a gate of the transistor T2.

The main feature of the present invention resides in that the n-th basiccircuit 113-n includes the transistor T5A which is the low voltageapplication switching element, and the transistor T5B which is the firstlow voltage application on control element. The basic clock signalV_(n+2) is input to the input terminal of the transistor T5B. At timing(timing to change from the signal high period to the signal low period)when the voltage at the gate signal G_(n) changes from the high voltageto the low voltage, that is, at timing when the basic clock signalV_(n+2) changes from the low voltage to the high voltage, the transistorT5B outputs the high voltage of the basic clock signal V_(n+2) to thenode N3, and the node N3 changes from the low voltage to the highvoltage. The transistor T5B becomes in the on state prior to thattiming, and outputs the high voltage of the basic clock signal V_(n+2)to the node N3. However, the transistor T5B has only to become in the onstate at least at the above timing. Hence, at the timing when the gatesignal G_(n) changes from the high voltage to the low voltage, thetransistor T5A turns on, and outputs the low voltage of the low voltageline V_(GL) to the output terminal OUT. The transistor T5A outputs thelow voltage to the output terminal OUT, thereby being capable of stablychanging the voltage to be applied to the corresponding gate signallines 105 from the high voltage to the low voltage more steeply, thatis, in a shorter time. That is, the blunting of the falling waveform ofthe gate signal G_(n) is suppressed. With the provision of thetransistor T5A, the element size of the transistor T5 which is the lowvoltage application switching element can be reduced, and the powerconsumption can be reduced. The low voltage line V_(GL) that ismaintained at the low voltage which is a constant voltage is connectedto the input terminal of the transistor T5A. Hence, unlike thetransistor T5, even if the transistor T5A is in the off state over thesignal low period, since the voltage to be applied to the input terminaldoes not change, a charge and discharge current hardly flows into thetransistor T5A. Hence, the provision of the transistor T5A hardlycontributes to an increase in the power consumption.

Because the node N3 changes from the low voltage to the high voltagesteeply, not the gate signal G_(n+2) but the basic clock signal V_(n+2)which is an external signal is used. As compared with the risingwaveform of the gate signal, the rising waveform of the basic clocksignal V_(n+2) is remarkably inhibited from being blunted, and the basicclock signal V_(n+2) remarkably steeply changes from the low voltage tothe high voltage. However, when the basic clock signal V_(th) is inputdirectly to the node N3 without the provision of the transistor T5B, thenode N3 cyclically repeats the low voltage and the high voltage. Thetransistor T5A cyclically turns on over the signal low period, and athreshold voltage V_(th) of the transistor T5A is shifted to a positiveside. When the threshold voltage V_(th) is shifted to the positive side,the transistor T5A does not stably turn on at timing when the gatesignal G_(n) changes from the high voltage to the low voltage, andcannot sufficiently output the low voltage to the output terminal OUT,which is not desirable. Hence, the transistor T5B that is the first lowvoltage application on control element is disposed in the n-th basiccircuit 113-n of the present invention. The transistor T5B becomes inthe on state prior to the timing when the gate signal G_(n) changes fromthe high voltage to the low voltage. The transistor T5B that becomesstably in the on state at the timing when the gate signal G_(n) changesfrom the high voltage to the low voltage outputs the high voltage of thebasic clock signal V_(n+2) to the node N3. That is, the basic clocksignal V_(n+2) cyclically becomes high voltage, and the high voltage isapplied to the gate of the transistor T5B in a period when the basicclock signal V_(n|2) becomes high voltage according to the signal highperiod of the gate signal G_(n), and the voltage of the basic clocksignal V_(n+2) is output to the node N3. Also, in the period when thebasic clock signal V_(n+2) becomes high voltage, the transistor T5B isin the off state, and the node N3 is blocked from the basic clock signalV_(n+2). The basic clock signal is input to the input terminal of thetransistor T5B, like the input terminal of the transistor T5. However,the transistor T5 becomes in the on state, and applies the voltage ofthe basic clock signal to the gate signal line. On the other hand, thetransistor T5B becomes in the on state, and merely applies the voltageof the basic clock signal to the node N3. In this example, as comparedwith the gate signal line, a parasitic capacitance generated in the nodeN3 is remarkably small. Hence, the input basic clock signal cyclicallybecomes high voltage together, but a load exerted on the transistor T5Bis small unlike the transistor T5. For that reason, since the elementsize of the transistor T5B can be reduced, the power consumption in thetransistor T5B is small, and not problematic.

FIG. 5 is a timing chart representing drive operation of the gate signalline drive circuit 104 according to this embodiment, and illustrateschanges of basic clock signals V_(n), V_(n+2) V_(n+4) the gate signalG_(n), and the nodes N1 _(n), N2 _(n), N1 _(n+2), N3 _(n) in time. Onecycle T of four-phase basic clock signals is four clocks, the changes intime illustrated in FIG. 5 are illustrated with one clock as a unit, andthe corresponding clocks are defined as periods P1 to P6. As describedabove, one clock is two horizontal scanning periods (2H periods). In theperiod P1 and the previous periods, the node N1 and the node N2 aremaintained at the low voltage and the high voltage, respectively.

As illustrated in FIG. 4, the input terminal IN3 is connected to thegate and the input terminal of the transistor T1 (diode connection), andthe node N1 is connected to the output terminal of the transistor T1.The gate signal G_(n−2) output by the (n−2)-th basic circuit 113-(n−2)is input to the input terminal IN3. Since the gate signal G_(n−2)becomes high voltage in the period P2 illustrated in FIG. 5, thetransistor T1 turns on, the transistor T1 applies the high voltage ofthe gate signal G_(n−2) to the node N1, and the node N1 changes from thelow voltage to the high voltage, at a start time of the period P2. Sincethe node N1 becomes high voltage, the transistor T5 turns on, and thetransistor T5 outputs the voltage of the basic clock signal V_(n) to theoutput terminal OUT.

Also, the input terminal IN3 is connected to a gate of a transistor T7,the low voltage line V_(GL) is connected to an input terminal of thetransistor T7, and the node N2 is connected to an output terminal of thetransistor T7. At a start time of the period P2, the transistor T7 turnson, the transistor T7 outputs the low voltage of the low voltage lineV_(GL) to the node N2, and the node N2 changes from the high voltage tothe low voltage. Hence, the transistors T2 and T6 turn off.

The node N1 is connected to a gate of a transistor T4, the low voltageline V_(GL) is connected to an input terminal of the transistor T4, andthe node N2 is connected to an output terminal of the transistor T4.Since the node N1 becomes high voltage in the period P2, the transistorT4 becomes in the on state, and outputs the low voltage of the lowvoltage line V_(GL) to the node N2. Hence, in a period when the node N1is high voltage, that is, in the periods P2 to P4, the transistor T4 ismaintained in the on state, and the node N2 is maintained at the lowvoltage.

In the period P3 that is signal high period, the node N1 is maintainedat the high voltage, and the transistor T5 is maintained in the onstate. The basic clock signal V_(n) becomes high voltage in the periodP3. Hence, in the period P3, the high voltage of the basic clock signalV_(n) is output from the output terminal OUT through the transistor T5as the gate signal G_(n).

In this example, because the threshold voltage V_(th) is actuallypresent in the transistor T1, the node N1 becomes a voltage obtained bysubtracting the threshold voltage V_(th) of the transistor T1 from thehigh voltage of the gate signal G_(n−2) in the period P2. In thisvoltage, there is a possibility that the transistor T5 cannotsufficiently turn on in the period P3 which is the signal high period.Therefore, the boost capacitor C1 is arranged to connect the gate of thetransistor T5 and the output terminal in the gate signal line highvoltage supply circuit 12. When it comes to the period P3, the gatesignal Gn−2 changes to the low voltage, and the transistor T1 turns off.However, the node N1 is maintained at the high voltage, and thetransistor T5 is maintained in the on state. In the period P3, the highvoltage of the basic clock signal V_(n) is applied to the outputterminal OUT, and the node N1 is boosted to a higher voltage by acapacitive coupling of the boost capacitor C1. This voltage is called“bootstrap voltage”.

Also, in the period P3 and the previous periods illustrated in FIG. 5,the node N3 is maintained at the low voltage. The gate signal G_(n+2) ofthe (n+2)-th basic circuit 113-(n+2) starts the signal high period afterone clock (start of the period P4) from a start of the signal highperiod (start of the period P3) of the gate signal G_(n). Also, asillustrated in FIG. 5, the node N1 _(n+2) becomes high voltage in theperiods P3 to P5. The node N1 _(n+2) is connected to the gate of thetransistor T5B, and the transistor T5B becomes in the on state in theperiods P3 to P5, and outputs the voltage of the basic clock signalV_(n+2) to the node N3.

At an end time of the period P3, the basic clock signal V_(n) changesfrom the high voltage to the low voltage. In this situation, asdescribed above, the node N1 is maintained at the high voltage, and thenode N2 is maintained at the low voltage. That is, the transistor T5 isin the on state, and the transistor T6 is in the off state. In thisembodiment, the node N1 _(n+2) is connected to the gate of transistorT5B, and as illustrated in FIG. 5, the node N1 _(n+2) becomes highvoltage in the periods P3 to P5, and in the periods, the transistor T5Bbecomes in the on state, and the transistor T5B outputs the voltage ofthe basic clock signal V_(n+2) to the node N3. At a start time of theperiod P4, the basic clock signal V_(n+2) changes from the low voltageto the high voltage, and the node N3 changes from the low voltage to thehigh voltage. Hence, the transistor T5A turns on at the start time ofthe period P4, and outputs the low voltage of the low voltage lineV_(GL) to the output terminal OUT.

As illustrated in FIG. 5, the node N1 _(n+2) is boosted to the bootstrapvoltage in the period P4. Hence, the node N1 _(n+2) in the period P4becomes a voltage higher than a sum of the threshold voltage V_(th) ofthe transistor T5B and the high voltage of the basic clock signalV_(n+2), and the transistor T5B becomes sufficiently in the on state inthe period P4. For that reason, the node N3 steeply changes from the lowvoltage to the high voltage, and the high voltage at the node N3 canreach substantially the same voltage as the high voltage of the basicclock signal V_(n+2). Hence, the low voltage can be more stably appliedto the corresponding gate signal line 105 at the start time of theperiod P4 than a case in which the transistor T5A turns on according toa gate signal in a subsequent stage, as disclosed in JP 2011-85663 A.

Also, in the period P5, the transistor T5B becomes in the on state, andthe transistor T5B outputs the basic clock signal V_(n+2) to the nodeN3, but the basic clock signal V_(n+2) becomes low voltage. Therefore,the node N3 becomes low voltage in the period P5. In this embodiment,the basic clock signal V_(n+4) is input to the gate of the transistorT5C, the basic clock signal V_(n+4) becomes high voltage in the periodP5, and the transistor T5C becomes in the on state. Hence, in the periodP5, the transistor T5C outputs the low voltage of the low voltage lineV_(GL) to the node N3. Then, even after the period P6, the basic clocksignal V_(n+4) cyclically becomes high voltage, and the transistor T5Cbecomes cyclically in the on state, and outputs the low voltage of thelow voltage line V_(GL) to the node N3. Hence, since the node N3 is heldat the low voltage over the signal low period, the threshold voltageV_(th) of the transistor T5A is inhibited from being shifted to thepositive side. Hence, at timing when the gate signal G_(n) changes fromthe high voltage to the low voltage, the transistor T5A can stably turnon, and output the low voltage to the output terminal OUT.

As illustrated in FIG. 4, the input terminal IN4 is connected to a gateof a transistor T9, the low voltage line V_(GL) is connected to an inputterminal of the transistor T9, and the node N1 is connected to an outputterminal of the transistor T9. The gate signal G_(n+4) output by the(n+4)-th basic circuit 113-(n+4) is input to the input terminal IN4.Since the gate signal G_(n+4) becomes high voltage in the period P5illustrated in FIG. 5, the transistor T9 turns on, outputs the lowvoltage of the low voltage line V_(GL) to the node N1, and the node N1changes from the high voltage to the low voltage, at a start time of theperiod P5. With the above operation, the transistor T5 turns off. At thesame time, the transistor T4 also turns off.

As illustrated in FIG. 4, the input terminal IN2 is connected to a gateand an input terminal of a transistor T3 (diode connection), and thenode N2 is connected to an output terminal of the transistor T3. Thebasic clock signal V_(b+4) is input to the input terminal IN2. Since thebasic clock signal V_(n+4) becomes high voltage in the period P5illustrated in FIG. 5, the transistor T3 turns on, the transistor T3outputs the high voltage to the node N2, and the node N2 changes fromthe low voltage to the high voltage, at a start time of the period P5.Since the node N2 becomes high voltage, the transistors T2 and T6 turnon. Also, a retentive capacitor C3 is arranged to connect the node N2and the low voltage line V_(GL), and the retentive capacitor C3 ischarged at the high voltage in the period P5.

Thereafter, even after the basic clock signal V_(n+4) becomes lowvoltage in the period P6, and the transistor T3 turns off, the node N2is maintained at the high voltage by the retentive capacitor C3.Further, since the basic clock signal V_(n+4) cyclically becomes highvoltage to continue to cyclically charge the retentive capacitor C3, thenode N2 is maintained at the high voltage, and the transistors T2 and T6are maintained in the on state. The transistor T6 outputs the lowvoltage of the low voltage line V_(GL) to the output terminal OUT, andholds the voltage of the corresponding gate signal line 105 at the lowvoltage. The transistor T2 outputs the low voltage of the low voltageline V_(GL) to the node N1, and holds the voltage of the correspondinggate signal line 105 at the low voltage.

FIG. 6 is a diagram illustrating a signal waveform of a gate signalaccording to this embodiment. FIG. 6 illustrates signal waveforms of thegate signal G_(n) output by the n-th basic circuit 113-n according tothis embodiment illustrated in FIG. 4. FIG. 6 illustrates the signalwaveforms when a channel width of the transistor T5 decreases from 3500μm to 1500 μm at the intervals of 500 μm whereas a channel width of thetransistor T5A increases from 0 to 2000 μm at the intervals of 500 μm.As with the rising waveform of the gate signal illustrated in FIG. 17,the rising waveform of the gate signal G_(n) increases the blunting ofthe signal waveforms with a reduction in the channel width of thetransistor T5. However, even when the channel width of the transistor T5is set to 1500 μm, the signal high period of the gate signal G_(n) istwo horizontal scanning periods (2H periods), and in one horizontalscanning period (1H period) of a second half, pixels are written in thepixel circuits connected to the corresponding gate signal line 105. Withthe above operation, the high voltage of the gate signal G_(n) rises toa sufficiently saturated state, and the pixel writing is conductedwithout any problem.

On the contrary, unlike the falling waveform indicated by the dashedline in FIG. 17, in a falling waveform of the gate signal G_(n)indicated by a dashed line in FIG. 6, the blunting of the signalwaveform is inhibited from increasing, with the arrangement of thetransistor T5A even if the channel width of the transistor T5 isreduced. The channel width of the transistor T5 decreases from 3500 μmto 1500 μm, to thereby reduce the power consumption as described above.On the other hand, the channel width of the transistor T5A is set to2000 μm, but a charge and discharge current hardly flows in thetransistor T5A as described above. Also, the element size of thetransistor T5B can be reduced sufficiently for the transistor T5B thatis in the on state to charge the parasitic capacitor generated in thenode N3 in a short time. In this embodiment, the transistor T5B can bedesigned so that the parasitic capacitance of the node N3 is 0.8 pF, thechannel width of the transistor T5B is 100 μm, and the channel length is4 μm. Hence, the power consumption in the transistor T5B can be reduced.

The power consumption of the basic circuits 113 according to thisembodiment is represented in the following Table 1 as compared with thebasic circuits according to the related art illustrated in FIG. 16.Table 1 represents the basic circuit (related art circuit) according tothe related art in which the channel width of the transistor T5 is setto 3500 μm (the transistor T5A is not arranged), and the basic circuit(circuit in the first embodiment) according to this embodiment in whichthe channel width of the transistor T5 is set to 1500 μm, and thechannel width of the transistor T5A is set to 2000 μm. As illustrated inFIGS. 6 and 17, in those two circuits compared with each other, thefalling waveforms of the gate signal G_(n) are substantially identicalwith each other, and steeply change from the high voltage to the lowvoltage together. Nevertheless, the power consumption of the basiccircuit according to this embodiment is 30 mW, that is, can be reducedto about ⅔ of the power consumption, compared with the power consumptionof 44 mW of the basic circuit in the related art.

TABLE 1 Circuit in Related Art Circuit in Embodiment 1 Power Consumption44 mW 30 mW T5 Channel Width 3500 μm 1500 μm T5A Channel Width None 2000μm

The basic clock signal input to the gate signal line drive circuitaccording to this embodiment are 4-phase clock signals, but not limitedto this type, and may be m-phase (m is an integer equal to or higherthan 3) clock signals. The m-phase clock signals repeat m clocks as onecycle. In this embodiment, the basic clock signal V_(n|4) (third basicclock signal) that changes from the low voltage to the high voltage attiming when the basic clock signal V_(n+2) (second basic clock signal)output by the transistor T5B changes from the high voltage to the lowvoltage is input to the gate of the transistor T5C. The transistor T5Cturns on at the start time of the period P5, and the transistor T5Coutputs the low voltage of the low voltage line V_(GL) to the node N3.With the above operation, the node N3 can steeply change from the highvoltage to the low voltage at the start time of the period P5 whilereducing a load exerted on the transistor T5B. It is desirable that thebasic clock signal V_(n+4) is input to the gate of the transistor T5C,but the present invention is not limited to this configuration. Thetransistor T5C that is the first low voltage application off controlelement may be configured by any element that turns on after thetransistor T5B, which is the first low voltage application on controlelement, outputs the high voltage of the second basic clock signal tothe node N3, and outputs the low voltage to the node N3. The basic clocksignal may be another basic clock signal (for example, basic clocksignal V_(n+6)) that becomes high voltage in a period since the secondbasic clock signal changes from the high voltage to the low voltageuntil the second basic clock signal then changes to the high voltage.Also, the basic clock signal cyclically becomes high voltage, and thetransistor T5C cyclically becomes in the on state, and outputs the lowvoltage of the low voltage line V_(GL) to the node N3, and the node N3is stably maintained at the low voltage over the signal low period,which is therefore desirable. However, the signal input to the gate ofthe transistor T5C is not limited to the basic clock signal, but may be,for example, another gate signal (for example, gate signal G_(n+4)). Inparticular, since the gate signal G_(n+4) output by the (n+4)-th basiccircuit 113-(n+4) becomes high voltage in the period P5, the loadexerted on the transistor T5B can be reduced, which is thereforedesirable.

Second Embodiment

An n-th basic circuit 113-n according to a second embodiment of thepresent invention is different from that of the first embodiment in thata signal input to the gate of the transistor T5B, which is the first lowvoltage application on control element, is input from a node N1 _(n+1)of an (n+1)-th basic circuit 113-(n+1). Also, a gate signal line lowvoltage supply circuit 14 _(n) provided in the n-th basic circuit 113-nis arranged on a side of the display area 120 opposite to the maincircuit of the n-th basic circuit 113-n. The other structures of thegate signal line drive circuit 104 according to this embodiment areidentical with those of the first embodiment.

FIG. 7 is a schematic diagram illustrating a configuration of a gatesignal line drive circuit 104 according to this embodiment. The gatesignal line drive circuit 104 according to this embodiment includes aneven shift register circuit 112A that outputs gate signals to respectiveeven-numbered gate signal lines 105 (400 lines), and an odd shiftregister circuit 112B that outputs gate signals to respectiveodd-numbered gate signal lines 105 (400 lines). The even shift registercircuit 112A includes 400 even basic circuits, and the odd shiftregister circuit 112B includes 400 odd basic circuits. The even shiftregister circuit 112A includes an even shift register main circuitportion 112A1 having main circuits of the even basic circuits, and aneven shift register sub-circuit portion 112A2 having a gate signal linelow voltage supply circuit 14 of the even basic circuits. The odd shiftregister circuit 112B includes an odd shift register main circuitportion 112B1 having main circuits of the odd basic circuits, and an oddshift register sub-circuit portion 112B2 having a gate signal line lowvoltage supply circuit 14 of the odd basic circuits. As illustrated inFIG. 7, the odd shift register sub-circuit portion 112B2 and the evenshift register main circuit portion 112A1 are arranged on a left side ofthe display area 120 in order, and the even shift register sub-circuitportion 112A2 and the odd shift register main circuit portion 112B1 arearranged on a right side of the display area 120 in order.

FIG. 8 is a circuit diagram illustrating a basic circuit 113 accordingto this embodiment. FIG. 8 schematically illustrates an area VIIIindicated by a dashed line of FIG. 7. An upper stage of FIG. 8illustrates an n-th basic circuit 113-n, and a lower stage of FIG. 8illustrates an (n+1)-th basic circuit 113-(n+1). As described above, themain circuit of the n-th basic circuit 113-n is arranged on the leftside of the display area 120, and indicated as 113-n in FIG. 8. The gatesignal line low voltage supply circuit 14 of the n-th basic circuit113-n is arranged on the right side of the display area 120, andindicated as 14 _(n) in FIG. 8. The (n+1)-th basic circuit 113-(n+1) isreversed in arrangement, but identical in the other configurations withthe n-th basic circuit 113-n.

The n-th basic circuit 113-n according to this embodiment is differentfrom that in the first embodiment in that the gate signal line lowvoltage supply circuit 14 _(n) is arranged on an opposite side of thedisplay area 120, the gate signal line low voltage supply circuit 14_(n) further includes an output terminal OUT3, and the output terminalOUT3 is connected to the output terminal of the transistor T5A. Asillustrated in FIG. 8, the output terminal OUTS is connected to thecorresponding gate signal line 105. Also, as described above, the inputterminal IN6 connected to the gate of the transistor T5B is connectedwith the node N1 _(n+1) of the (n+1)-th basic circuit 113-(n+1). Also,with the above arrangement of the gate signal line low voltage supplycircuit 14 _(n), a line that connects the gate of the transistor T5B andthe node N1 _(n+1) can be shortened.

FIG. 9 is a timing chart representing drive operation of the gate signalline drive circuit 104 according to this embodiment, and illustrateschanges of the basic clock signals V_(n), V_(n+2), V_(n+4), the gatesignal G_(n), the nodes N1 _(n), N2 _(n), Na_(n), the basic clocksignals V_(n+1), V_(n+3), V_(n+5), the gate signal G_(n+1), and thenodes N1 _(n+1), N2 _(n+1), N3 _(n+1) in time. As illustrated in FIG. 9,the gate signal G_(n+1) output by the (n+1)-th basic circuit 113-(n+1)is a gate signal that changes to the high voltage later than the gatesignal G_(n) output by the n-th basic circuit 113-n by half clock. Thenode N1 _(n+1) becomes high voltage from a center of the period P2 to acenter of the period P5. Hence, the transistor T5B according to thisembodiment becomes in the on state in the above period. A time at whichthe period P4 starts is timing when the basic clock signal V_(n+2) inputto the input terminal of the transistor T5B changes from the low voltageto the high voltage, and the time is a center of a period (from a centerof the period P3 to a center of the period P4) during which the nodebecomes a bootstrap voltage that is boosted by a capacitive coupling ofthe boost capacitor C1.

It is desirable that the transistor T5B become sufficiently in the onstate, and the voltage of the basic clock signal V_(n+2) is output tothe node N3, at the start time of the period P4. The gate of thetransistor T5B according to the first embodiment is connected with thenode N1 _(n+2) of the (n+2)-th basic circuit 113-(n+2), and the starttime of the period P4 is a start of a period during which the voltage ofthe node N1 _(n+2) becomes the bootstrap voltage. However, in fact, ittakes a finite time to change from a normal high voltage to a bootstrapvoltage by the capacitive coupling of the boost capacitor C1, and thenode N1 _(n+2) is not yet sufficiently boosted to the bootstrap voltageat the start time of the period P4. On the contrary, the node N1 _(n+1)connected to the gate of the transistor T5B according to this embodimentis sufficiently boosted to the bootstrap voltage at the start time ofthe period P4, and the node N1 _(n+1) is higher than a sum of thethreshold voltage V_(th) of the transistor T5B and the high voltage ofthe basic clock signal V_(n+2) The transistor T5B is sufficiently in theon state at the start time of the period P4. Hence, as compared with thefirst embodiment, the node N3 steeply changes from the low voltage tothe high voltage, and the high voltage at the node N3 can arrive atsubstantially the same voltage as the high voltage of the basic clocksignal V_(n+2) Hence, at the start time of the period P4, the transistorT5A can more stably supply the low voltage to the corresponding gatesignal line 105, and can more suppress the blunting of the fallingwaveform of the gate signal G_(n) output from the output terminal OUT.

In this example, it is assumed that the n-th basic circuit 113-n is afirst basic circuit. In the first embodiment, when it is assumed thatthe (n+2)-th basic circuit 113-(n+2) is a second basic circuit, thesignal high period of the second basic circuit starts at a time (startof the period P4 illustrated in FIG. 5) later than the start (start ofthe period P3 illustrated in FIG. 5) of the signal high period of thefirst basic circuit by one clock. On the other hand, in the secondembodiment, when it is assumed that the (n+1)-th basic circuit 113-(n+1)is the second basic circuit, the signal high period of the second basiccircuit starts at a time (center of the period P3 illustrated in FIG. 9)later than the start (start of the period P3 illustrated in FIG. 9) ofthe signal high period of the first basic circuit by half clock. In thefirst and second embodiments, the node N1 of the second basic circuit isconnected to the gate (control terminal) of the transistor T5B (thefirst low voltage application on control element) of the first basiccircuit. In this way, since the node N1 is sufficiently high voltage inthe signal high period of the basic circuit in the second basic circuit,it is desirable that assuming that the basic circuit in which the signalhigh period of the gate signal starts within one clock after the startof the signal high period (the period P3 indicated in FIGS. 5 and 9) ofthe first basic circuit (the gate signal G_(n)) is the second basiccircuit, the node N1 of the second basic circuit is connected to thegate of the transistor T5B. The transistor T5B is sufficiently in the onstate at a time (the start time of the period P4 indicated in FIGS. 5and 9) when the basic clock signal V_(n+2) input to the transistor T5Bof the first basic circuit changes from the low voltage to the highvoltage, and the node N3 can steeply change from the low voltage to thehigh voltage. In the gate signal line drive circuit according to thefirst and second embodiments, the basic clock signal having 2H periodsas one clock is used. However, the present invention is not limited tothis configuration, and may use a basic clock signal having a largernumber of horizontal scanning periods (for example, 4H periods) as oneclock. When the larger number of horizontal scanning periods is set asone clock, there are present the larger number of basic circuits inwhich the signal high period of the gate signal starts within one clockafter the start of the signal high period of the first basic circuit(the gate signal G_(n)). For that reason, an appropriate basic circuitcan be selected as the second basic circuit from the above basiccircuits can be connected to the node N1 of the second basic circuit,and the gate of the transistor T5B of the n-th basic circuit 113-n. Inthis example, the n-th basic circuit 113-n has been described as thefirst basic circuit. Alternatively, the respective basic circuits may beset as the first basic circuits, and a basic circuit suitable for thefirst basic circuits may be set as the second basic circuit withoutdepending on the specific value of n.

Third Embodiment

A gate signal line drive circuit 104 according to a third embodiment ofthe present invention is different in the configuration of the basiccircuits 113 from that of the first or second embodiment, and alsodifferent in the basic clock signal to be input from that of the firstor second embodiment. On the other hand, the other structures areidentical with those of the first or second embodiment.

FIG. 10 is a circuit diagram of an n-th basic circuit 113-n according tothis embodiment. The n-th basic circuit 113-n according to thisembodiment includes a main circuit portion 15, and a gate signal linelow voltage supply circuit 14.

First, the main circuit portion 15 of the n-th basic circuit 113-n willbe described. The n-th basic circuit 113-n according to this embodimentis different from the n-th basic circuit 113-n according to the firstembodiment illustrated in FIG. 4 in that the input terminal IN2, thetransistors T3, T7, and the retentive capacitor C3 are not provided.Instead, the n-th basic circuit 113-n further includes input terminalsINA, INB, and INC, and basic clock signals V_(n+2), V_(n+4), and V_(n+6)are input to the input terminals INA, INB, and INC, respectively. Also,the n-th basic circuit 113-n further includes transistors T6A, T6B, T6C,and a buffer capacitor C2. The buffer capacitor C2 is connected betweenthe input terminal IN1 and the node N2. All of input terminals of thetransistors T6A, T6B, and T6C are connected to the low voltage lineV_(GL), and all of output terminals of the transistors T6A, T6B, and T6Care connected to the output terminal OUT. Gates of the transistors T6A,T6B, and T6C are connected to the input terminals INA, INB, and INC,respectively.

FIG. 11 is a timing chart representing drive operation of the gatesignal line drive circuit 104 according to this embodiment. FIG. 11illustrates changes of the basic clock signals V_(n), V_(n+2), V_(n+4),V_(n+6), the gate signal G_(n), and the nodes N1 _(n), N2 _(n), N1_(n+2), N3 _(n) in time.

As in the first embodiment, in the period P1 and the previous periods,the node N1 is maintained at the low voltage. At the start time of theperiod P2, the gate signal G_(n−2) output by the (n−2)-th basic circuit113-(n−2) changes from the low voltage to the high voltage, and the nodeN1 changes from the low voltage to the high voltage. At the start timeof the period P5, the gate signal G_(n|4) output by the (n+4)-th basiccircuit 113-(n+4) changes from the low voltage to the high voltage, andthe node N1 changes from the high voltage to the low voltage. Hence, asin the first embodiment, the node N1 is at high voltage in the periodsP2 to P4, and the transistor T5 is in the on state in those periods. Thetransistor T5 outputs the voltage of the basic clock signal V_(n) to theoutput terminal OUT (corresponding gate signal line 105). In the periodP3 (signal high period), the basic clock signal V_(n) becomes highvoltage, and the gate signal G_(n) output from the output terminal OUTbecomes high voltage.

In the periods P2 to P4, since the node N1 becomes high voltage, thetransistor T4 becomes in the on state, and outputs the low voltage ofthe low voltage line V_(GL) to the node N2. Hence, the node N2 ismaintained at the low voltage, and the transistors T2 and T6 become inthe off state. In the period P3, the basic clock signal V_(n) input tothe input terminal IN1 becomes high voltage, but the node N2 ismaintained at the low voltage by charging the buffer capacitor C2. Inthe period P5, the node N1 becomes low voltage, and the transistor T4becomes in the off state. Thereafter, the node N2 rises through thebuffer capacitor C2 according to the basic clock signal V_(n) thatbecomes cyclically high voltage, and becomes high voltage. The node N2becomes high voltage, as a result of which the transistors T2 and T6become in the on state, the transistor T2 outputs the low voltage of thelow voltage line V_(GL) to the node N1, and the transistor T6 outputsthe low voltage of the low voltage line V_(GL) to the output terminalOUT (corresponding gate signal line 105).

In addition to the transistor T6, the transistors T6A, T6B, and T6Cbecome in the on state when the basic clock signals V_(n+2), V_(n+4),and V_(n+6) become high voltage, and output the low voltage of the lowvoltage line V_(GL) to the output terminal OUT (corresponding gatesignal line 105). Hence, the gate signal G_(n) is stably maintained atthe low voltage over the signal low period.

At the start time of the period P4 (at timing when the gate signal G_(n)changes from the high voltage to the low voltage), the transistor T6Aturns on, and outputs the low voltage of the low voltage line V_(GL) tothe output terminal OUT (corresponding gate signal line 105). However,as described above, because the transistor T6A is cyclically in the onstate, the threshold voltage V_(th) of the transistor T6A is shifted tothe positive side, and at the timing when the gate signal G_(n) changesfrom the high voltage to the low voltage, the transistor T6A does notstably turn on, and the transistor T6A cannot sufficiently output thelow voltage to the output terminal OUT.

Subsequently, a description will be given of the gate signal line lowvoltage supply circuit 14 of the n-th basic circuit 113-n. As in thefirst embodiment, the n-th basic circuit 113-n according to thisembodiment includes the gate signal line low voltage supply circuit 14,and at the start time of the period P4, the transistor T5B stably turnson by the node N1 _(n+2), and the node N3 steeply changes from the lowvoltage to the high voltage. As a result, at the start time of theperiod P4, the transistor T5A stably turns on, and can sufficientlyoutput the low voltage of the low voltage line V_(GL) to the outputterminal OUT. That is, the present invention is not limited to the gatesignal line drive circuit according to this embodiment, but can beextensively applied to various gate signal line drive circuits.

In this embodiment, the node N1 _(n+2) of the (n+2)-th basic circuit113-(n+2) is connected to the gate of the transistor T5B. However, it isneedless to say that the present invention is not limited to thisconfiguration. As in the second embodiment, the node N1 _(n+1) of the(n+1)-th basic circuit 113-(n+1) may be connected to the gate of thetransistor T5B. Alternatively, the node N1 of the basic circuit in whichthe signal high period of the gate signal starts within one clock afterthe start of the signal high period (the period P3) of the gate signalG_(n) may be connected to the gate of the transistor T5B.

Fourth Embodiment

A gate signal line drive circuit 104 according to a fourth embodiment ofthe present invention is different in a configuration in which basiccircuits 113 are bidirectional from that in the first to thirdembodiments, and a gate signal and a basic clock signal to be input aredifferent from those in the first to third embodiments. However, theother configurations are identical with those in any one of the first tothird embodiments.

FIG. 12 is a circuit diagram of an n-th basic circuit 113-n according tothis embodiment. Unlike the n-th basic circuit 113-n according to thefirst embodiment illustrated in FIG. 4, an n-th basic circuit 113-naccording to this embodiment further includes input terminals IN3A,IN4A, IN5A, IN6A, and IN7A. A gate signal G_(n|2), a gate signalG_(n−4), a basic clock signal V_(n−2) (fourth basic clock signal), anode N1 _(n−2), and a basic clock signal V_(n) (first basic clocksignal) are input to the input terminals IN3A, IN4A, IN5A, IN6A, andIN7A, respectively. In this example, the basic clock signal V_(n−2)(fourth basic clock signal) is a clock signal that becomes high voltagein a clock previous to a clock in which the basic clock signal V_(n)(first basic clock signal) becomes high voltage. Further, the n-th basiccircuit 113-n further includes transistors T1A, T5BA, T5CA, T7A, andT9A. The transistors T1A, T7A, and T9A have the same function as that ofthe transistors T1, T7, and T9 in forward scanning, in reverse scanning,respectively. Also, the transistors T1A, T7A, and T9A do not contributeto a voltage change of the nodes in the forward scanning. On thecontrary, the transistors T1, T7, and T9 do not contribute to a voltagechange of the nodes in the reverse scanning. The transistor T5BA is asecond low voltage application on control element, and the transistorT5CA is a second low voltage application off control element. Both ofthe transistors T5BA and T5CA are disposed in the gate signal line lowvoltage supply circuit 14.

The order of increasing a value of “n” of the n-th basic circuit 113-nis the forward order, and scanning in which the gate signals become highvoltage in the forward order is the forward scanning. On the contrary,the order of decreasing the value of “n” is opposite to the forwardorder, and defined as the reverse order, and the scanning in which thegate signals become high voltage in the reverse order is the reversescanning. In this embodiment, in the forward scanning, as in the firstto third embodiments, the basic clock signals V_(n−2), V_(n), V_(n|2),and V_(n|4) become high voltage in the stated order. However, in thereverse scanning, the basic clock signals V_(n−2), V_(n), V_(n+2), andV_(n+4) become high voltage in an order reverse to the forward order.That is, the basic clock signals V_(n+4) V_(n+2), V_(n), and V_(n−2)become high voltage in the stated order. Also, because the inputterminal IN3A of an 800^(th) basic circuit 113-800, and the inputterminal IN3A of a 799^(th) basic circuit 113-799 have no correspondinggate signals, auxiliary signals V_(ST1) and V_(ST2) are input to thoserespective input terminals. Also, because the input terminals IN4A ofthe first basic circuit 113-1 to the fourth basic circuit 113-4 have nogate signals, four dummy circuits are disposed in the respective basiccircuits. In the gate signal line drive circuit according to thisembodiment, the basic clock signals V_(n−2), V_(n), V_(n+2), and V_(n+4)become high voltage in the stated order to drive the forward scanning.The basic clock signals V_(n−2), V_(n), V_(n+2), and V_(n+4) become highvoltage in the order reverse to the forward order to drive the reversescanning. Thus, the bidirectional scanning is enabled.

The input terminal IN5A is connected to an input terminal of thetransistor T5BA, the node N3 is connected to an output terminal of thetransistor T5BA, and the input terminal IN6A is connected to a gate ofthe transistor T5BA. Also, the low voltage line V_(GL) is connected toan input terminal of the transistor T5CA, the node N3 is connected to anoutput terminal of the transistor T5CA, and the input terminal IN7A isconnected to a gate of the transistor T5CA. When the node N1 _(n−2) ofthe (n−2)-th basic circuit 113-(n−2) is at high voltage, the transistorT5BA becomes in the on state, and outputs the voltage of the basic clocksignal V_(n−2) to the node N3. Also, when the basic clock signal V_(n)is high voltage, the transistor T5CA becomes in the on state, andoutputs the low voltage of the low voltage line V_(GL) to the node N3.

FIG. 13 is a timing chart representing drive operation of the gatesignal line drive circuit 104 in the forward scanning according to thisembodiment. FIG. 13 illustrates changes of the basic clock signalsV_(n−2), V_(n), V_(n+2), V_(n+4), the gate signal G_(n), and the nodesN1 _(n), N2 _(n), N1 _(n−2), N1 _(n+2) N3 _(n) in time. The voltagechanges of the nodes N1 and N2 are identical with those in the firstembodiment. The node N3 becomes high voltage in the periods P2 to P4,and becomes low voltage in the other periods.

In the period P1 and the previous periods, the node N3 is maintained atthe low voltage. The node N1 _(n−2) of the (n−2)-th basic circuit113-(n−2) becomes high voltage in the periods P1 to P3, as illustratedin FIG. 13. The node N1 _(n−2) is connected to the gate of thetransistor T5BA, and the transistor T5BA becomes in the on state in theperiods P1 to P3, and outputs the voltage of the basic clock signalV_(n−2) to the node N3. At the start time of the period P2, the basicclock signal V_(n−2) changes from the low voltage to the high voltage.Hence, at least at timing when the basic clock signal V_(n−2) changesfrom the low voltage to the high voltage, the transistor T5BA becomes inthe on state, and outputs the voltage of the basic clock signal V_(n−2)to the node N3. As illustrated in FIG. 13, the node N3 becomes highvoltage, and the transistor T5A becomes in the on state, and outputs thelow voltage of the low voltage line V_(GL) to the output terminal OUT(corresponding gate signal line 105). The basic clock signal V_(n)becomes high voltage in the period P3, and the transistor T5CA becomesin the on state, and outputs the low voltage of the low voltage lineV_(GL) to the node N3. The node N3 becomes stably low voltage in theperiod P3 by the aid of the transistor T5CA. Further, the transistorsT5B and T5C are driven in the same manner as that in the firstembodiment, as a result of which the node N3 becomes high voltage in theperiod P4, and becomes low voltage in the period P5 and the subsequentperiods. Since the basic clock signal V_(n) becomes cyclically highvoltage, the transistor T5CA becomes cyclically in the on state, andoutputs the low voltage of the low voltage line V_(GL) to the node N3,as with the transistor T5C.

In this example, it is assumed that the n-th basic circuit 113-n is afirst basic circuit. In this embodiment, when it is assumed that the(n−2)-th basic circuit 113-(n−2) is a third basic circuit, the signalhigh period of the third basic circuit starts at a time earlier than thestart (the start of the period P3) of the signal high period of thefirst basic circuit (gate signal G_(n)) by one clock (start of theperiod P2). As with the above second basic circuit, the third basiccircuit is not limited to this configuration. A basic circuit isdesirable in which the signal high period of the gate signal startswithin one clock before the start of the signal high period of the firstbasic circuit.

As illustrated in FIG. 12, the low voltage line V_(GL) is connected toan input terminal of the transistor T9A, the node N1 is connected to anoutput terminal of the transistor T9A, and the input terminal IN4A isconnected to a gate of the transistor T9A. A gate signal G_(n−4) outputby an (n−4)-th basic circuit 113-(n−4) is input to the gate of thetransistor T9A. In the period P1, the gate signal G_(n−4) becomes highvoltage, and the transistor T9A becomes in the on state, and outputs thelow voltage of the low voltage line V_(GL) to the node N1. However,since the node N1 is maintained at the low voltage, there is no changein the voltage at the node N1.

As illustrated in FIG. 12, the input terminal IN3 is connected to a gateand an input terminal of the transistor T1A (diode connection), and thenode N1 is connected to an output terminal of the transistor T1A. Theinput terminal IN3A is connected to a gate of the transistor T7A, thelow voltage line V_(GL) is connected to an input terminal of thetransistor T7A, and the node N2 is connected to an output terminal ofthe transistor T7A. In the period P4 illustrated in FIG. 13, the gatesignal G_(n+2) becomes high voltage, and the transistor T1A becomes inthe on state, and outputs the high voltage of the gate signal G_(n+2) tothe node N1. However, since the node N1 is maintained at the highvoltage, there is no change in the voltage at the node N1. Likewise, inthe period P4, the transistor T7A becomes in the on state, and outputsthe low voltage of the low voltage line V_(GL) to the node N2. However,since the node N2 is maintained at the low voltage, there is no changein the voltage at the node N2.

FIG. 14 is a timing chart representing drive operation of the gatesignal line drive circuit 104 in the reverse scanning according to thisembodiment. FIG. 14 illustrates changes of the basic clock signalsV_(n−2), V_(n), V_(n+2), V_(n+4), the gate signal G_(n), and the nodesN1 _(n), N2 _(n), N1 _(n−2), N1 _(n+2), N3 _(n) in time.

As described above, the second basic clock signal is a clock signal thatbecomes high voltage later than the first basic clock signal (the basicclock signal V_(n)) by one clock. The fourth basic clock signal is aclock signal that becomes high voltage earlier than the first basicclock signal (the basic clock signal V_(n)) by one clock. In the forwardscanning, the second basic clock signal is the basic clock signal andV_(n+2), the fourth basic clock signal is the basic clock signalV_(n−2). In the reverse scanning, the second basic clock signal is thebasic clock signal V_(n−2), and the fourth basic clock signal is thebasic clock signal V_(n+2). Hence, in this embodiment, the second basicclock signal is input to the input terminal of the transistor T5B (firstlow voltage application on control element) in the forward scanning, andthe fourth basic clock signal is input thereto in the reverse scanninginstead of the second basic clock signal. Likewise, the fourth basicclock signal may be input to the input terminal of the transistor T5BA(second low voltage application on control element) in the forwardscanning, and the second basic clock signal may be input thereto in thereverse scanning instead of the fourth basic clock signal.

In the period P1 and the previous periods, the node N3 is maintained atthe low voltage. The node N1 _(n+2) becomes high voltage in the periodsP1 to P3, as illustrated in FIG. 14, and the transistor T5B becomes inthe on state in the periods P2 to P4. The basic clock signal V_(n+2)becomes high voltage in the period P2, and the transistor T5B outputsthe high voltage of the basic clock signal V_(n+2) to the node N3 in theperiod P2. The basic clock signal V_(n) becomes high voltage in theperiod P3, and the transistor T5CA becomes in the on state, and outputsthe low voltage of the low voltage line V_(GL) to the node N3. That is,in both of the forward scanning and the reverse scanning, the transistorT5CA becomes in the on state in the period P3 according to the basicclock signal V_(n), and can stably maintain the voltage of the node N3at the low voltage. As illustrated in FIG. 14, the node N1 _(n−2)becomes high voltage in the periods P3 to P5, and the transistor T5BAbecomes in the on state in the periods P3 to P5. The basic clock signalV_(n−2) becomes high voltage in the period P4, and the transistor T5BAoutputs the high voltage of the basic clock signal V_(n−2) to the nodeN3 in the period P4. In the period P5, the basic clock signal V_(n+4)becomes high voltage, and the transistor T5C becomes in the on state,and outputs the low voltage of the low voltage line V_(GL) to the nodeN3. After the period P6, the basic clock signals V_(n) and V_(n+4)become cyclically high voltage, and the transistors T5CA and T5C becomecyclically in the on state, and output the low voltage of the lowvoltage line V_(GL) to the node N3. Hence, even in the reverse scanning,the node N3 becomes high voltage in the periods P2 and P4, and becomeslow voltage in the other periods.

As described above, the transistors T1A, T7A, and T9A have the samefunction as that of the transistors T1, T7, and T9 in forward scanning,in reverse scanning, respectively. At the start time of the period P2,the gate signal G_(n+2) output by the (n+2)-th basic circuit 113-(n+2)changes from the low voltage to the high voltage, and the transistor T1Aturns on. The transistor T1A applies the high voltage of the gate signalG_(n+2) to the node N1, and the node N1 changes from the low voltage tothe high voltage. Likewise, at the start time of the period P2, thetransistor T7A turns on, the transistor T7A applies the low voltage ofthe low voltage line V_(GL) to the node N2, and the node N2 changes fromthe high voltage to the low voltage. Also, at the start time of theperiod P5, the gate signal G_(n−4) output by the (n−4)-th basic circuit113-(n−4) changes from the low voltage to the high voltage, and thetransistor T9A turns on. The transistor T9A applies the low voltage ofthe low voltage line V_(GL) to the node N1, and the node N1 changes fromthe high voltage to the low voltage.

Also, as described above, the transistors T1, T7, and T9 do notcontribute to the voltage changes at the nodes in the reverse scanning.In the period P1, the gate signal G_(n+4) becomes high voltage, and thetransistor T9 becomes in the on state, and outputs the low voltage ofthe low voltage line V_(GL) to the node N1. However, since the node N1is maintained at the low voltage, there is no change in the voltage atthe node N1. In the period P4, the gate signal G_(n−2) becomes highvoltage, and the transistor T1 becomes in the on state, and outputs thehigh voltage of the gate signal G_(n−2) to the node N1. However, sincethe node N1 is maintained at the high voltage, there is no change in thevoltage at the node N1. Likewise, in the period P4, the transistor T7Abecomes in the on state, and outputs the low voltage of the low voltageline V_(GL) to the node N2. However, since the node N2 is maintained atthe low voltage, there is no change in the voltage at the node N2.

In the forward scanning, in a clock (the period P4 indicated in FIG. 13)after the signal high period (the period P3 indicated in FIG. 13) of thegate signal G_(n), the transistor T5B outputs the high voltage of thebasic clock signal V_(n+2) to the node N3. Further, in a subsequentclock (the period P5 indicated in FIG. 13), the transistor T5C outputsthe low voltage of the low voltage line V_(GL) to the node N3 accordingto the high voltage of the basic clock signal V_(n+4). Also, in thereverse scanning, in a clock (the period P4 indicated in FIG. 14) afterthe signal high period (the period P3 indicated in FIG. 14) of the gatesignal G_(n), the transistor T5BA outputs the high voltage of the basicclock signal V_(n−2) to the node N3. Further, in a subsequent clock (theperiod P5 indicated in FIG. 14), the transistor T5C outputs the lowvoltage of the low voltage line V_(GL) to the node N3 according to thehigh voltage of the basic clock signal V_(n+4)(=V_(n−4)). In thisembodiment, four-phase basic clock signals are used, and the basic clocksignal V_(n+4) is shifted in phase from the basic clock signal V_(n) byπ. Hence, in both of the forward scanning and the reverse scanning, thebasic clock signal V_(n+4) is a clock signal that becomes high voltagelater than the basic clock signal V_(n) by two clocks, and thetransistor T5C becomes in the on state according to the high voltage ofthe basic clock signal V_(n+4) in the period P5 indicated in FIGS. 13and 14, and outputs the low voltage of the low voltage line V_(GL) tothe node N3. As a result, the node N3 becomes stably low voltage in theperiod P5. That is, the transistor T5C can perform the same function inboth of the forward scanning and the reverse scanning. The same isapplied to the transistor T3.

As described above, in the gate signal line drive circuit according tothe present invention, in order to enable the bidirectional scanning,the basic clock signals of four or larger phases are necessary, and avalue of “m” of the m clocks configuring one cycle of the basic clocksignal becomes 4 or larger (m≧4). If “m” is larger than 4, the basicclock signal input to the gate of the transistor T5C may be a clocksignal that becomes high voltage since the second basic clock signalchanges from the high voltage to the low voltage until the fourth basicclock signal then changes from the low voltage to the high voltage.Also, in both of the forward scanning and the reserve scanning, thetransistor T5C turns on after the high voltage of the second basic clocksignal has been output to the node N3, and outputs the low voltage tothe node N3. However, the present invention is not limited to thisconfiguration. A third low voltage application on control element thatis connected in parallel to the first low voltage application on controlelement (the transistor T5C) may be further provided in the node N3. Inthe forward scanning, after the high voltage of the second basic clocksignal has been output to the node N3, the first low voltage applicationon control element turns on, and outputs the low voltage to the node N3.In the reverse scanning, after the high voltage of the second basicclock signal has been output to the node N3, the third low voltageapplication on control element turns on, and outputs the low voltage tothe node N3. It is desirable that the signals input to the respectivecontrol terminals of the first to third low voltage application oncontrol elements are basic clock signals, but not limited to thissignal. For example, the gate signal G_(n+4) may be input to the controlterminal of the first low voltage application on control element, andthe gate signal G_(n−4) may be input to the control terminal of thethird low voltage application on control element.

In the display device according to the embodiments of the presentinvention, as illustrated in FIG. 2, the liquid crystal display deviceof the IPS system has been described. Alternatively, the display deviceaccording to the present invention may be configured by a liquid crystaldisplay device of another drive system such as a VA (vertically aligned)liquid crystal display device, or a TN (twisted nematic) liquid crystaldisplay device, or may be configured by another display device such asan organic EL display device. FIG. 15 is a conceptual diagram of anequivalent circuit of a TFT substrate 102 provided in a liquid crystaldisplay device according to another example of the embodiment of thepresent invention. FIG. 15 illustrates an equivalent circuit of the TFTsubstrate 102 provided in the VA liquid crystal display device and theTN liquid crystal display device. In the VA liquid crystal displaydevice and the TN liquid crystal display device, the common electrode111 is disposed on the filter substrate 101 that faces the TFT substrate102. The present invention can be extensively applied to another gatesignal line drive circuit and another display device without beinglimited to the above embodiments.

While there have been described what are at present considered to becertain embodiments of the invention, it will be understood that variousmodifications may be made thereto, and it is intended that the appendedclaims cover all such modifications as fall within the true spirit andscope of the invention.

What is claimed is:
 1. A gate signal line drive circuit including aplurality of basic circuits that output respective gate signals whichbecome an ON voltage in a signal ON period which is cyclically repeated,and become an OFF voltage in a signal OFF period which is a period otherthan the signal ON period to corresponding gate signal lines, each ofthe basic circuits comprising: an ON voltage application switchingelement having an input terminal, a control terminal, and an outputterminal electrically connecting to the gate signal line; an OFF voltageapplication switching element having an input terminal, a controlterminal, and an output terminal electrically connecting to the gatesignal line; a first OFF voltage application on control element havingan input terminal, a control terminal, and an output terminal, theoutput terminal being electrically connected to the control terminal ofthe OFF voltage application switching element; and a basic clock signalline applying a basic clock signal and electrically connecting to theinput terminal of the ON voltage application switching element and thecontrol terminal of the first OFF voltage application on controlelement, wherein an ON voltage is applied to the control terminal of theON voltage application switching element according to the signal ONperiod, to output the basic clock signal to the corresponding gatesignal line, wherein an ON voltage is applied to the control terminal ofthe OFF voltage application switching element at timing to change fromthe signal ON period to the signal OFF period, to output the OFF voltageto the corresponding gate signal line, and wherein the first OFF voltageapplication on control element outputs the basic clock signal to thecontrol terminal of the OFF voltage application switching element attiming when the basic clock signal changes from the OFF voltage to theON voltage.
 2. The gate signal line drive circuit according to claim 1,wherein the plurality of basic circuits include a first basic circuit,and a second basic circuit, wherein the signal ON period of the secondbasic circuit starts within one clock after a start of the signal ONperiod of the first basic circuit, and wherein the control terminal ofthe ON voltage application switching element in the second basic circuitis connected to the control terminal of the OFF voltage application oncontrol element in the first basic circuit.
 3. The gate signal linedrive circuit according to claim 1, wherein each of the basic circuitsfurther comprises a first OFF voltage application off control elementthat turns on after the first OFF voltage application on control elementoutputs the ON voltage of the basic clock signal to the control terminalof the OFF voltage application switching element, and outputs the OFFvoltage to the control terminal of the OFF voltage application switchingelement.
 4. A gate signal line drive circuit including a plurality ofbasic circuits that output respective gate signals which become an ONvoltage in a signal ON period which is cyclically repeated, and becomean OFF voltage in a signal OFF period which is a period other than thesignal ON period to corresponding gate signal lines, each of the basiccircuits comprising: an ON voltage application switching element havingan input terminal, a control terminal, and an output terminalelectrically connecting to the gate signal line; an OFF voltageapplication switching element having an input terminal, a controlterminal, and an output terminal electrically connecting to the gatesignal line; a first OFF voltage application on control element havingan input terminal, a control terminal, and an output terminal, theoutput terminal being electrically connected to the control terminal ofthe OFF voltage application switching element; and a basic clock signalline applying a basic clock signal to the input terminal of the ONvoltage application switching element and the control terminal of thefirst OFF voltage application on control element, wherein an ON voltageis applied to the control terminal of the ON voltage applicationswitching element according to the signal ON period, to output the basicclock signal to the corresponding gate signal line, wherein an ONvoltage is applied to the control terminal of the OFF voltageapplication switching element at timing to change from the signal ONperiod to the signal OFF period, to output the OFF voltage to thecorresponding gate signal line, and wherein the first OFF voltageapplication on control element outputs the basic clock signal to thecontrol terminal of the OFF voltage application switching element attiming when the basic clock signal changes from the OFF voltage to theON voltage.
 5. The gate signal line drive circuit according to claim 4,wherein the plurality of basic circuits include a first basic circuit,and a second basic circuit, wherein the signal ON period of the secondbasic circuit starts within one clock after a start of the signal ONperiod of the first basic circuit, and wherein the control terminal ofthe ON voltage application switching element in the second basic circuitis connected to the control terminal of the OFF voltage application oncontrol element in the first basic circuit.
 6. The gate signal linedrive circuit according to claim 4, wherein each of the basic circuitsfurther comprises a first OFF voltage application off control elementthat turns on after the first OFF voltage application on control elementoutputs the ON voltage of the basic clock signal to the control terminalof the OFF voltage application switching element, and outputs the OFFvoltage to the control terminal of the OFF voltage application switchingelement.